<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Assembly | David Shu-Yu Wu</title><link>https://aurivelle.github.io/tags/assembly/</link><atom:link href="https://aurivelle.github.io/tags/assembly/index.xml" rel="self" type="application/rss+xml"/><description>Assembly</description><generator>Hugo Blox Builder (https://hugoblox.com)</generator><language>en-us</language><lastBuildDate>Sat, 04 Jul 2026 00:00:00 +0000</lastBuildDate><image><url>https://aurivelle.github.io/media/icon_hu_982c5d63a71b2961.png</url><title>Assembly</title><link>https://aurivelle.github.io/tags/assembly/</link></image><item><title>Multiplying Not-So-Big Integers with FFTs</title><link>https://aurivelle.github.io/projects/nttbignummul/</link><pubDate>Sat, 04 Jul 2026 00:00:00 +0000</pubDate><guid>https://aurivelle.github.io/projects/nttbignummul/</guid><description>&lt;p&gt;This first-author research project, &lt;strong&gt;Finding and Pushing the Crossover on Large Modern OoO ARM CPUs&lt;/strong&gt;, studies where NTT-based multiplication becomes practical for not-so-big integer sizes. The paper is available as &lt;strong&gt;
&lt;/strong&gt; and was accepted for presentation at the &lt;strong&gt;CHES 2026 Poster Session&lt;/strong&gt;.&lt;/p&gt;
&lt;p&gt;The project develops two generations of constant-time NTT-based multiplication for Cortex-A76. The second generation targets smaller operand sizes through tighter range bounds, redesigned 256/512-point NTT organization, fused reconstruction, and shorter carry and instruction-dependency chains.&lt;/p&gt;
&lt;h3 id="key-features"&gt;Key Features&lt;/h3&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;NEON-optimized NTT kernels:&lt;/strong&gt; Developed constant-time fused NTT kernels in AArch64 assembly using ARM NEON instructions.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Multiplication pipeline:&lt;/strong&gt; Combined Barrett and Montgomery arithmetic, Good&amp;rsquo;s trick, CRT reconstruction, and chunking and dechunking.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Crossover result:&lt;/strong&gt; The second-generation two-unknown-input multiplier outperforms target-tuned variable-time GMP by &lt;strong&gt;6.25% at 5,632 bits&lt;/strong&gt; and &lt;strong&gt;16.66% at 8,448 bits&lt;/strong&gt;, placing the observed crossover at or below 5,632 bits.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Montgomery multiplication:&lt;/strong&gt; The one-known-input implementation improves over OpenSSL&amp;rsquo;s Neon path by &lt;strong&gt;5.19%-44.40%&lt;/strong&gt; across the evaluated 5,120-10,240-bit sizes.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;OpenSSL integration:&lt;/strong&gt; End-to-end RSA verification and encryption improve by &lt;strong&gt;15.98%-51.58%&lt;/strong&gt; across RSA-5120, RSA-6144, RSA-8192, and RSA-10240.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Formal verification:&lt;/strong&gt; Verified optimized assembly kernels with CryptoLine for algebraic correctness, range safety, and equivalence after Slothy scheduling, then used HOL Light to compose higher-level multiplication specifications.&lt;/li&gt;
&lt;/ul&gt;</description></item><item><title>Cryptography Engineering on Cortex-M4</title><link>https://aurivelle.github.io/projects/m4optimization/</link><pubDate>Thu, 02 Jul 2026 00:00:00 +0000</pubDate><guid>https://aurivelle.github.io/projects/m4optimization/</guid><description>&lt;p&gt;This project is the final project for &lt;strong&gt;Cryptography Engineering (2025 Fall)&lt;/strong&gt; at National Taiwan University, lectured by Matthias J. Kannwischer. It focuses on aggressive performance optimization of two modern cryptographic primitives on resource-constrained embedded systems.&lt;/p&gt;
&lt;p&gt;The project implements highly optimized versions of:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;ML-KEM (FIPS 203):&lt;/strong&gt; NIST&amp;rsquo;s lattice-based post-quantum key encapsulation mechanism&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;X25519 (ECDH25519):&lt;/strong&gt; Elliptic Curve Diffie-Hellman key exchange&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;Target Platform:&lt;/strong&gt; ARM Cortex-M4 microcontroller&lt;br&gt;
&lt;strong&gt;Constraints:&lt;/strong&gt; Constant-time execution, strict code-size budgets for NTT routines&lt;/p&gt;
&lt;h3 id="key-optimizations"&gt;Key Optimizations&lt;/h3&gt;
&lt;h4 id="x25519-ecdh25519"&gt;X25519 (ECDH25519)&lt;/h4&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Finite Field Arithmetic (mod p = 2^255 - 19):&lt;/strong&gt; Hand-optimized assembly for &lt;code&gt;fe25519_mul&lt;/code&gt; (field multiplication) and &lt;code&gt;fe25519_sqr&lt;/code&gt; (field squaring), achieving 81-85% cycle reduction.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Constant-Time Scalar Multiplication:&lt;/strong&gt; No secret-dependent branches or table indexing to prevent timing side-channel attacks.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Fixed-Base Acceleration:&lt;/strong&gt; Window method with precomputed tables using constant-time selection, reducing fixed-base scalar multiplication by up to &lt;strong&gt;94%&lt;/strong&gt; against the course baseline.&lt;/li&gt;
&lt;/ul&gt;
&lt;h4 id="ml-kem-fips-203"&gt;ML-KEM (FIPS 203)&lt;/h4&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;NTT/iNTT Kernels:&lt;/strong&gt; Optimized Number-Theoretic Transform operations with reduced memory traffic, layer fusion, and loop unrolling, achieving &lt;strong&gt;2.85-3.79x speedup&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Polynomial Arithmetic (mod q = 3329):&lt;/strong&gt; Leveraged ARMv7E-M DSP instructions (SIMD 16-bit operations) for packed polynomial addition and subtraction, achieving &lt;strong&gt;2-2.2x speedup&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Code-Size Budgeting:&lt;/strong&gt; NTT routines implemented under strict per-function size constraints while maintaining performance.&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Course-Baseline Result:&lt;/strong&gt; Reduced the cycle count of ML-KEM &lt;code&gt;poly_ntt&lt;/code&gt; by up to &lt;strong&gt;62%&lt;/strong&gt; under the same benchmarking setup.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;This project demonstrates deep understanding of low-level optimization, cryptographic algorithm engineering, and secure implementation practices on embedded ARM platforms.&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;
&lt;/strong&gt;&lt;/li&gt;
&lt;/ul&gt;</description></item></channel></rss>